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How to deal with clock trace in pcb layout to avoid ckt EMI?

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hellen10

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help:the emi of clock

hi
in my board, the emi question of the clock is very obviously, the radiate of the clock is very large. how can I deal with the clock trace in pcb layout to avoiding the clock EMI? thanks.
 

Re: help:the emi of clock

You have several options all of which can be combined.

First, use a clock with the longest rise and fall times that will still function in your circuit. You can cause this by putting a small resistor in series with the clock driver output.

Next you can put the clock oscillator in the center of the board with the traces going out in all directions. This will partially null out the radiation.

Even more drastic is to put the clock traces and all high speed traces on an inner layer of the PC board between two ground planes.
 

Re: help:the emi of clock

use clock jitter!!!
 

help:the emi of clock

first, you can use a series damping resistor.
second, you can use a proper parallel cap.
 

Re: help:the emi of clock

Radiate of the clock may be because of CURRENT LOOP on your PCB. Check all return currents. If you use synchronous devices without filter capacitor located close to these devices it can looks like clock frequency radiation.
 

Re: help:the emi of clock

thank you very much.
if i need to use a guard ground around the clock trace in multilayers?
 

Re: help:the emi of clock

The return path for the clock should be directly under the clock line (ground plane). On general principles you should put ground in all vacant areas and connect ground layers together with vias. This also helps prevent board warping and coupling of the clock into other traces.
 

Re: help:the emi of clock

hellen10 said:
hi
in my board, the emi question of the clock is very obviously, the radiate of the clock is very large. how can I deal with the clock trace in pcb layout to avoiding the clock EMI? thanks.

Please specify how you determine the EMI is came from clock. I wonder that someone always ignore the buses or long trace, it always emit the radiation as form of harmonics of clock!
 

help:the emi of clock

in design with large ic (mcu or fpga) which works in synchonous with master clock power source trace with higher switching current (in sync with clock) tend to radiate much noise then clock line, consider better decoupling cap. and ferrite bead.
 

Re: help:the emi of clock

You can try to add some cap to smooth the waveform and it also can filter some high frequency.
Impedance match is an important point.
 

help:the emi of clock

you do not need to use a guard ground around the clock trace in multilayers. FYR
 

Re: help:the emi of clock

The EMI problem is reduced if you use MICRO ISLAND technique for your design. the noise sources are isolated on small ground islands .
.
use of multilayer boards also reduces the EMI problem 8)
 

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