I only add period and offset on my code, but there is one path don't satisfy the period constraints, and several path don't satisfy the offset out constraints. I don't know how to deal with it. can anybody give me some advice?
check the timing report first. If the period constraints violation is small, try use more powerful synthesis option. otherwise try to modify the rtl code.
For the offset constraints violation, check if you register in/out the io register.
I remember ISE has build-in timing analysis tools.
Run it and then the tools suggest some methods to improve the violation path. Though it may not really help you.
everytime after synthesize, xst will give a reference frequency, it's so low, but in my timing report, I can see the period constraint is satisfied. and this period is more higher than the xst result, I am puzzled whether this xst frequency is usable?
XST gives only a rough estimate of the expected speed, because the device hasn't been routed yet. After routing, the actual timing may be faster or slower than XST's estimate.
If you have a small complete example project that demonstrates your timing difficulty, you can post it here, and maybe someone can help you improve it.
Re: how to deal the path who can't satisfy timing constraint
normaly when you add global constraints such as the period constraint, it contraints all the design and so it will be more difficult to meet the constraints.. so try to add path specific timing contraints for the paths that didn't meet the timing.... check if these paths are multi cycle paths, false paths.... and so on...