Hi i can't generate sign adder
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module AD3(D1,D2,D3,Do);
input [15:0] D1;
input [15:0] D2;
input [15:0] D3;
output [16:0] Do;
reg [16:0]Do;
always @ (D1 or D2 or D3)
Do=D1+D2-D3;
endmodule
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i using Do=D1+D2-D3; but when i view RTL schmetic it show unsign adder
how to i write it
Signed operations are supported since Verilog 2001 released. Plz confirm your synthesis tool can support the signed operation. If so, you can use the 'signed' keyword. otherwise, you may have to follow the coding style suggested by *fangll