Re: VERILOG RPM problem
HI jelydonut!
you 're helpful really and I'm pleased to see that elektroda members are so friendly and dedicated to other members problems.
yes the code is synthesizable, in fact it is working OK, the only thing is that RLOC and some others constraints in VERILOG doesn't work properly.
Cos of my genius CTO I will have to find the solution. :?
looking on this case all the people who say that Verilog is better than VHDL please think twice before saying so. Also I don't know why but xilinx & VHDL seams to me a perfect couple. :wink:
bart