[SOLVED] how to create an instance/object for SystemC model in SystemVerilog Class

[prashantsid]

I am trying to use a SystemC reference model in a UVM based test-bench.
what can be the possible way for creating an instance of SystemC module (class) in a SystemVerilog class.
I have tried using SC_MODULE_EXPORT but it allows me to create an instance in Verilog/SystemVerilog module as design entities, not as class objects.
I prefer not to use predefined libraries from Cadence/Mentor (UVM ML or UVMC)
Also if there is any tool dependent function, please let me know.
Tools used - ModelSim 10.1c

Thanks

 

[dave_59]

There is no way to instantiate a SC_Module inside a SV class because there is no way to instantiate any kind of module; Verilog, SC, SV, VHDL entity inside an SV class. An SV class is a dynamic object. A module in any language is a static object

You should review UVM Connect from Mentor. https://verificationacademy.com/topics/verification-methodology/uvm-connect. This library is open-source and not dependent on any tool.

You could type wrapping a driver/monitor around your SC module, just as if it were a SV module.

 

[prashantsid]

You could type wrapping a driver/monitor around your SC module, just as if it were a SV module.

Can you please explain it in detail.
And does this 'wrapping a driver/monitor around SC module' needs UVM Connect library.

P.S. - I am using a UVM based testbench, I know that UVMC fits the bill but somehow I choose not to use the predefined library if there is an other way around.

- - - Updated - - -

You should review UVM Connect from Mentor. https://verificationacademy.com/topics/verification-methodology/uvm-connect. This library is open-source and not dependent on any tool.

While using UVM Connect library I am facing an issue. Please refer to another post https://www.edaboard.com/threads/278814/

 

[dave_59]

If your SC module has compatible ports that could be instantiated into a pure Verilog/SystemVerilog design, then you don't need UVMC. Assuming you can make your SC module pin-compatible with your RTL DUT module, then you can set up your UVM stimulus to drive both modules, then have two monitors on the modules which send transactions to compare in your scoreboard.

If your module has TLM port and you don't to use the UVMC library, then you will have to re-invent what it does yourself.

Hope that helps; I don't have time to explain in any more detail.

 

[prashantsid]

Thanks Dave for guiding me through this.

 

[Jayakirthi]

If your SC module has compatible ports that could be instantiated into a pure Verilog/SystemVerilog design, then you don't need UVMC. Assuming you can make your SC module pin-compatible with your RTL DUT module, then you can set up your UVM stimulus to drive both modules, then have two monitors on the modules which send transactions to compare in your scoreboard.

If your module has TLM port and you don't to use the UVMC library, then you will have to re-invent what it does yourself.

Hope that helps; I don't have time to explain in any more detail.

Hi,

What do you mean by SC module having compatible ports that could be instantiated in Verilog/SystemVerilog? Is there any way to interface UVM and SC at signal level?

 

[dave_59]

You can mix SystemC, Verilog, SystemVerilog, VHDL design units all in the same simulation if you follow your tools rules for compatible ports. See your tools documentation for mixed language simulation. Once you do that, your SC Module will appear to be no different than a Verilog module, then you can use similar UVM drivers/monitors to communicate with your SC module in the same way that you communicate with your Verilog module. There is nothing special you have to do with the UVM to accomplish this. You just need a simulator, like Questa, that supports mixed language SC/SV module instantiation.