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I assume you have already written your Verilog or VHDL code. If you've never written any HDL, try this simple Verilog 8-bit counter. Save it to a filename such as top.v
module top (clk, count);
output reg [7:0] count=0;
always @ (posedge clk) begin
count <= count + 1;
1. Launch ISE Project Navigator (I'm using ISE Foundation 8.1i).
2. Click File -> New Project -> enter desired projectname/location -> HDL -> Next.
3. Choose your device type -> Next.
4. Click Next to skip the Create New Source dialog.
5. Click Add Source -> navigate to your Verilog/VHDL source file -> Open -> Next.
6. Click Finish -> Ok to accept all your project creationg settings.
7. In the Processes tab, double-click Generate Programming File.
8. In a few seconds (or minutes or hours), it should synthesize, then place-and-route, and then create a configuration file that you can download to your device.
9. To see the routed chip layout, in the Processes tab, expand Implement Design, then expand Place & Route, then double-click View/Edit Routed Design (FPGA Editor). To zoom-in, use Ctrl-Shift-click-drag. To zoom out press F6.
My example does not constrain any pin locations, so ISE will choose them semi-randomly.