How to create a xilinx project ,file and how to synthesis it

[shobha]

doubt.....

i have a doubt on xilinx.my query is,
how to create a xilinx project ,file and how to synthesis it.help me.

 

[no_mad]

doubt.....

Hi shobha,

First u need xilinx ISE webpack version and u can download it for free from xilinx website.

Then, u read the user guide on how to use it or u can try xilinx tutorial.

Next, if u face any probs or errors u can write to this group or u go to xilinx mysupport website to get the answer to ur probs.

https://www.xilinx.com/support/mysupport.htm

Hope it helps... n enjoy learning
-no_mad

 

[echo47]

doubt.....

I assume you have already written your Verilog or VHDL code. If you've never written any HDL, try this simple Verilog 8-bit counter. Save it to a filename such as top.v

module top (clk, count);
  input             clk;
  output reg  [7:0] count=0;

  always @ (posedge clk) begin
    count <= count + 1;
  end
endmodule

1. Launch ISE Project Navigator (I'm using ISE Foundation 8.1i).
2. Click File -> New Project -> enter desired projectname/location -> HDL -> Next.
3. Choose your device type -> Next.
4. Click Next to skip the Create New Source dialog.
5. Click Add Source -> navigate to your Verilog/VHDL source file -> Open -> Next.
6. Click Finish -> Ok to accept all your project creationg settings.
7. In the Processes tab, double-click Generate Programming File.
8. In a few seconds (or minutes or hours), it should synthesize, then place-and-route, and then create a configuration file that you can download to your device.
9. To see the routed chip layout, in the Processes tab, expand Implement Design, then expand Place & Route, then double-click View/Edit Routed Design (FPGA Editor). To zoom-in, use Ctrl-Shift-click-drag. To zoom out press F6.

My example does not constrain any pin locations, so ISE will choose them semi-randomly.