how to create a signal from a file, to be used as a test signal for VHDL testbench?

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Fractional-N

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Hi,
is there a way to create an input signal to a VHDL testbench from a HEX file?

also, if you now some useful software that can accept as input a video stream and generate the HEX file from it please tell me
 

1. yes you can. Look into the std.textio package (there are many tutorials on the internet).
2. You may be able to do it with matlab.
 
thanks but i douldn't find any good tutorial. I need to write a testbench in VHDL for Xilinx (Xilinx ISE software). can you please provide me a link?
 
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