user982
Newbie level 1
Hi,
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM : t_array := ("10001","10010","10100", ...
Thanks
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM : t_array := ("10001","10010","10100", ...
Thanks