How to create a ROM using Verilog code?

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Hi,

I have this vhdl code for creating ROM. How could be in verilog?

architecture a of test is

-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM : t_array := ("10001","10010","10100", ...

Thanks
 

Re: ROM in verilog

If you use ROM for emulation you can use this construct for example:

reg [4:0] ROM [63:0];
initial
begin
ROM[0]=5'h10;
ROM[1]=5'h3;
...
ROM[63]=5'h1F;
end

Or
reg [4:0] ROM [63:0];
always@(negedge reset)
if(~reset)
begin
ROM[0]<=5'h10;
ROM[1]<=5'h3;
...
ROM[63]<=5'h1F;
end

But you should use Macro from FAB if you're going to synthesize real ASIC.
 

Re: ROM in verilog

Setting the ROM content in an initial block is the exact equivalent to the VHDL initialized signal and should work with any device, that has ROM functionality. Setting the values in an explicite reset can prevent ROM inference, if the device hardware lacks a reset capability for the ROM.
 

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