How to create a frequency counter in verilog

[ntropy]

I need to create a frequency counter, reporting the duty cycle. Any input how to create this?

 

[bassa]

You may search the forum and Google to find more

Here some example for

regards
bassa

 

[ntropy]

I referenced your link and added it to my current project however I'm getting 0 as my output.

(top of project in the module input wire in_clock,)

wire resetn;
reg [2:0] in_clock_rsync;
wire in_clock_rise;
reg [13:0] count;
reg [13:0] f_measurment;

// Look for rising edge of in_clock
assign in_clock_rise = ~in_clock_rsync[1] & in_clock_rsync[0];

// Resynchronize in_clock to ref_clock domain
always @(posedge clk50)
in_clock_rsync <= {in_clock_rsync[1:0],in_clock};

always @(posedge clk50 or negedge resetn)
if(!resetn) begin
count <= 14'd0; // reset counter
f_measurment <= 14'd0; // reset output
end else begin
count <= count + 14'd1; // increment counter by default
if(in_clock_rise) begin
count <= 14'd0; // reset counter
f_measurment <= count; // determine output
end
end
/***** User Controls section *****/
wire [7:0] user_ctrl_en; // 8 seperate enables controlled via GUI
wire [15:0] user_ctrl; // 16-bit value entered via GUI
reg [127:0] user_status=0; // 16 bytes of status that reported back to GUI
wire user_ctrl_stb; // strobe to signal when user controls written

always @(posedge clk125)
if (user_ctrl_en[0]) begin user_status <={f_measurment};