How to create 4 Clock Cycle delay in design

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spartanthewarrior

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Hi all,

How can i create 4 clock cycle delay in my design.
 

Is this what you wanted? Note, you don't really need reset in the delay FFs.

always @(posedge clk) begin
wr_d1 <= #1 wr; // wr is the signal you want to delay
wr_d2 <= #1 wr_d1;
wr_d3 <= #1 wr_d2;
wr_d4 <= #1 wr_d3;
end
 

spartanthewarrior said:
Hi all,

How can i create 4 clock cycle delay in my design.
Click to expand...

Use a simple counter.
 

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