How to count number of '1's in std_logic_vector? (VHDL)

[uoficowboy]

Hi - in VHDL, if I have a std_logic_vector of an unknown size (set via a generic) - is there a way to count how many of the elements are equal to '1'?

Thanks!

-Michael

 

[permute]

You can always use a variable and a loop. (or a function).

in hardware, it should be similar to N 1-bit additions. the complexity should scale with around log2(N) levels of logic. I suspect an actual implementation on an FPGA would scale around log4(N) for most cases.

 

[uoficowboy]

You can always use a variable and a loop. (or a function).

in hardware, it should be similar to N 1-bit additions. the complexity should scale with around log2(N) levels of logic. I suspect an actual implementation on an FPGA would scale around log4(N) for most cases.

That would take at least N clock cycles to compute, right? Is there any way to do it instantly?

 

[vipinlal]

@uoficowboy : No, it wont take N clock cycles. What permute wrote is a correct method . This method will take N clock cycles only when the counting is done inside a process at a clock edge.
But if you use a function or a loop with a variable(note that you have to use variable here and not signal), then it will take place within one clock cycle.
But the number of resources used here will be more.And also the maximum operating freq may decrease depending on the size of the std_logic_vector.

See this link for logic resource usage for combinational loops:
https://vhdlguru.blogspot.com/2010/04/recursive-functions-in-vhdl.html


--vipin
https://vhdlguru.blogspot.com/

 

[permute]

Not sure the link is really the best example. I find far too many articles on that site to be incorrect, misleading, confusing, or dangerously misleading for the FPGA case.

in this case, the author compares the complexity of using a recursive function to something (it didn't seem to be specified). The logic generated seemed ideal for a v5/v6, but was deemed to use "more resources".

 

[TrickyDicky]

Just write VHDL to do what you want - let the synthesisor do all the work. Here is the function you want:

function count_ones(s : std_logic_vector) return integer is
  variable temp : natural := 0;
begin
  for i in s'range loop
    if s(i) = '1' then temp := temp + 1; 
    end if;
  end loop;
  
  return temp;
end function count_ones;

now you just need to call this function in a clocked process:

process(clk)
begin
  if rising_edge(clk) then
    n_bits <= count_ones(s);
  end if;
end process;