nainathakur1121
Newbie level 3
Hello,
I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding.
I want to use the same test bench for validation on FPGA. So the test bench needs to be synthesizable.
My query: Are there any other standard tools from vendors (like synopsys, cadence...) which can automatically
converts the behavioral test bench to synthesizable?
or Are there any scripts available to do so?
Thanks in advance!
I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding.
I want to use the same test bench for validation on FPGA. So the test bench needs to be synthesizable.
My query: Are there any other standard tools from vendors (like synopsys, cadence...) which can automatically
converts the behavioral test bench to synthesizable?
or Are there any scripts available to do so?
Thanks in advance!