convert std_logic_vector to std_logic
Hey try for it yourself ya...You will find errors.
Like I said,just see how I coded. Only Din,Dout corresponds to std_logic_vector(0 downto 0).These are generated from FIFO IP core.any values passed to Din or Dout must also be of same data type,otherwise it shows errors....
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entity SDR
PORT (
sclk : in std-logic;--codec clk
sdi : out std_logic; --data to codec
sdo : in std_logic; -- data from codec
din : in std-logic_vector(0 downto 0); ---FIFO data input
dout : out std_logic_vector(0 downto 0); --FIFO data output
wr_clk,rd_clk : out std_logic; -- Indpendant clk mode for FIFO stacking
wr_en,rd_en : out std_logic;-- enable pins
full,empty : std_logic --flags
);
architecture SDR of Behavioral is
signal count1,count2 : integer range 0 to 40 :=0;
begin
process(sclk) is
begin
if rising_edge(sclk) then
count1 <= count1+1;
case count1 is
when 0 => rd_en <= '1'; -- enable read data from fifo
when 1 => sdi <= din; -- start reading data and send it to sdi bus(codec)
when 3 => sdi <= din;
when 33 => count2 <= 0;
rd_en <= '0';
when 34 =>
count2 <= count2+1;
count1 <= 34;
case count2 is
when 0 => wr_en <= '1';
when 1 => dout <= sdo;
when 2 => dout <= sdo;
when 33 => count 1 <= 0;
wr_en <= '0';
when others => null;
end case;
when others => null;
end case;
end if;
end process;
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Here sdi is assigned to dout....But both are of std_logic and std_logi_vector(0 downto 0) type.If you pass values then it shows errors ..no use!....Got any idea?.