Hi, I am new to HDL. I have downloaded a verilog code for the CORDIC based implementation of FFT https://github.com/JoshuaEbenezer/FFT-cordic-HDL. A project_report.pdf file is also available in the given link. The design basically computes the 16 point Radix-2 DIF FFT algorithm. According to the manual (project report.pdf) the output should be obtained as 4683 + 6i, when xin1 to xin16 used are all 320. But, after giving xin1 to xin16 values as all 320, I am getting the output as
xout= 0000010000001100111110101010111011111101010011011111111110001101111111010100010100000010110001100000000100011001000000110101110111111010100111000000001000010110000000101011011100000100111110011111111101110011000001001111111000000011010100010000010110010111
But according to the manual file (page 9, Table 2) the output should be 4683 + 6i (first one, rest all are zeros). It will be very helpful to me if anybody tell me how can I convert xout values to 4683 + 6i.
xout has a size of
output signed [15:0] xout [0:15];
in other words if I display xout values in 16-bit wise
[255:240] xout to [15:0] xout
0000010000001100
1111101010101110
1111110101001101
1111111110001101
1111110101000101
0000001011000110
0000000100011001
0000001101011101
1111101010011100
0000001000010110
0000001010110111
0000010011111001
1111111101110011
0000010011111110
0000001101010001
0000010110010111
and in complex form the output should be [15:0] xout=4683 + 6i and the rest all are zeros.
I will request you please go to the code once, which is found in the link https://github.com/JoshuaEbenezer/FFT-cordic-HDL
None of those binary values matches 4683. There are also no zeros. So it is wrong anyway and does not need conversion to see. Moreover how come output is 256 bits for 16 data without defining word boundary..just serial stream is not realistic.