how to convert 10MHz clock to 1.024MHz

[arash rezaee]

Hi every one.
I want to convert 10MHz crystal clock to 1.024MHz. Some one told me I can do it with PLL but I don`t know how!!??
He sugested to me MC145152 PLL IC. Also, I read from this website that with DCM in FPGA we can create our clock but when I put input for 10MHz it said output can be from 18MHz to 300MHz. I need help and I really appreciate for your help.
Regards
Arash

 

[betwixt]

There are several ways, using a PLL you would have to divide 10MHz by 2500 to give 4KHz then multiply it by 256 to give 1.024MHz.
Possibly a dual modulus divider could do it more efficiently.

Brian.

 

[FvM]

A non-fractional (= not generating additional jitter) PLL would use 64/625 as smallest integer frequency ratio. If a FPGA implementation is an option, you'll preferable generate 128 MHz (64/5) by a PLL and implement a 1/25 post divider in logic fabric.

 

[arash rezaee]

Thanks for reply. I don`t have any idea about PLL. Can you explain more about PLL circuit ( maybe with schematic). So I can underestand how can confugure PLL IC to generate (64/5).
Regards
Arash

 

[goldsmith]

Dear Arash
Hi
Is it important to you , to create just 1.024 MHZ ? is there any problem with 1MHZ ?
Best Wishes
Goldsmith

 

[arash rezaee]

Dear Goldsmith

Yup. It is really important and I need 1.024MHZ ( Actually it is 1.048576MHz). It is really important to have such a frequency in my design.

Regards

 

[goldsmith]

Why not a micro controller ? you can achieve this frequency with that . but with PLL , i haven't any idea .
Good luck
Goldsmith

 

[arash rezaee]

well I need this frequency for a part of my design inside the FPGA and I have no Idea how to generate it. Can you let me know how can I do it with micro controller?

 

[RetroTechie]

Is it important to you , to create just 1.024 MHZ ? is there any problem with 1MHZ ?

Yup. It is really important and I need 1.024MHZ ( Actually it is 1.048576MHz).

:idea: The other way around: is that 10 MHz a given, or could that be changed? If yes, what's acceptable range?

 

[arash rezaee]

Hi. 10Mhz is not important. all available crystals can be placed. Just output frequency is important.

 

[RetroTechie]

2.097152 /2 = 1.048576
4.194304 /4 = 1.048576
22.00000 /21 = 1.047619 (within 0.1%, with discrete crystal circuit that includes a variable capacitor you might tune this).

 

[betwixt]

Hi. 10Mhz is not important. all available crystals can be placed. Just output frequency is important.

If the 10MHz isn't critical, use a 10.48576 MHz crystal and divide by 10.

Brian.

 

[FvM]

If an FPGA with PLL is used in the application, it's easy to generate the exact 1.024 MHz form a standard crystal. You don't need to think about appoximation in this case. There's also no "PLL design problem" involved, you parametrize the respective Core Generator or MegaWizard and that's it.