In case anyone is wondering, Shurik's Verilog code generates 357 pulses on signal C3_57 for every 1000 input clocks. The pulse spacing is non-uniform, of course.
I briefly described your code to help readers who don't know Verilog. I don't know if it will help ajaykumar988. He may require uniformly spaced pulses. Also, his "3.57" value seems suspicious to me - he may have rounded-off the common frequency "3.57954545...". But we don't know!
I briefly described your code to help readers who don't know Verilog. I don't know if it will help ajaykumar988. He may require uniformly spaced pulses. Also, his "3.57" value seems suspicious to me - he may have rounded-off the common frequency "3.57954545...". But we don't know!