Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to control a node

Status
Not open for further replies.

geozog86

Member level 3
Member level 3
Joined
Oct 24, 2010
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,774
How to change VDS/VDSSAT

Hello!

I have a funny very basic but very confusing situation.

photo.JPG

I have the circuit you see in the graph: a tail transistor M1 has a set gate voltage C, so it's acting as a current source.
The branch I care about has a current source (transistor M3, with gate voltage A set, so set vgs), so I know the current I am taking in this branch from the tail transistor.
Then I have the transistor M2, with externally set gate voltage B.
My understanding is that by having VB set, and current through M2 set, I'm setting TAIL voltage (so Vgs of M2 is the appropriate value).

Here's the fun: How do I control VD in order to change VDS of M2?

There are a few corners in which M2 enters linear region. In those corners resizing the transistor (I made L longer for example) changes VDS, but at the same time so does VDSSAT since VGS is changing, and I remain in linear. Plus that change only makes VTAIL change-VD stays pretty constant.

So (the general question is) how do I change VDS without changing VDSSAT? Or How do I control V at node D. Or how do I bring a transistor in saturation from linear with minimal changes?

((FYI there may be many ways, but I can't change for example biasing in node B....Unfortunately!))

Cheers for any kind of idea (circuit specific or general lesson on biasing, both will be appreciated)
 
Last edited:

Hi geozog86,

The problem you are facing is a general problem. This problem is caused because the node 'D' is a high impedance node. In any common source amplifiers with current source load the output node can not be controlled (search net / any book on CMOS amplifiers for more details). Even if you bias it properly at a particular PVT (process, voltage & temperature), it will definitely vary across PVT and force one of the MOSFETs in to linear region.

If your intention is to design an amplifier then better to shift to a single ended differential amplifier.

Note: (1) Fully differential or double ended differential amplifiers are also prone to same issue so a technique known as CMFB (Common Mode Feedback) is used to control the output DC level. (search net / any book on CMOS amplifiers for more details on CMFB)
(2) In CS amplifier also CMFB can be used but it will require the design of an OTA for the CMFB loop. Designing a complete OTA for a single stage amplifier does not make much sense. Better to shift for a differential amplifier.
(3) Simple CS stage is generally not used as a stand alone amplifier. It acts as a 2nd stage or 3rd stage of a differential amplifier to boost the overall gain.

Hope this will help ... :)
 
Thank you that's a very helpful generic approach.

I am obliged (work restrictions) to hide the "rest" of the circuit, but this is not a standalone amplifier, but part of a feedback loop.....That's why I mentioned that I'd like as few changes as possible-you're totally right that CMFB would solve that if that was used as an amp (standalone)....

My understanding is that I cannot do much about it, so perhaps I'll have to re-bias or change the size of the current source load to give it some headroom to work around this.....

I'll evaluate my risks! Thx for that!
 

Hi geozog86,

I under stand your work restriction..... :)

But again if the ckt is in a loop then the voltage in the high impedance node is controlled by the loop.
You can change / adjust the node voltage D either by suitably sizing or changing the next stage (load) bias requirement. But that might not be in your hand.
So you are right about that you have to re-bias / re-size. Even if you can not control the drain (node D) of a MOS but you can control the source there by increasing VDS .... :)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top