How to contrain the number of "1" of a bit-sequence in Systemverilog

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weben

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In my systemverilog testbench, I need to genrate a 32 bits sequence which randomly contains 5 to 27 bit "1". Can anyone help me to describe the constrant of this random bit-sequence? thanks a lot
 

Code: 
rand bit [31:0] value;

constraint random_bit_sequence {$countones(value) inside {[5:27]}; }
 
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    weben

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Thanks Dave,
It's really helpful. But $countones seems only works in Questa. VCS does not support using $contones in contstraint blocks in 2012.09 version.
 

You can try

Code: 
rand bit value[31:0];
constraint random_bit_sequence {value.sum() with (int'(item)) inside {[5:27]}; }
 
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    weben

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dave_59 said:
You can try

Code: 
rand bit value[31:0];
constraint random_bit_sequence {value.sum() with (int'(item)) inside {[5:27]}; }
Click to expand...

Thanks again. This one works in VCS.
 

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