How to contrain the number of "1" of a bit-sequence in Systemverilog

[weben]

In my systemverilog testbench, I need to genrate a 32 bits sequence which randomly contains 5 to 27 bit "1". Can anyone help me to describe the constrant of this random bit-sequence? thanks a lot

 

[dave_59]

rand bit [31:0] value;

constraint random_bit_sequence {$countones(value) inside {[5:27]}; }

 

[weben]

Thanks Dave,
It's really helpful. But $countones seems only works in Questa. VCS does not support using $contones in contstraint blocks in 2012.09 version.

 

[dave_59]

You can try

rand bit value[31:0];
constraint random_bit_sequence {value.sum() with (int'(item)) inside {[5:27]}; }

 

[weben]

You can try

rand bit value[31:0];
constraint random_bit_sequence {value.sum() with (int'(item)) inside {[5:27]}; }

Thanks again. This one works in VCS.