entity ANDGATE is
port (
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end entity ANDGATE;
architecture RTL of ANDGATE is
begin
O <= I1 and I2;
end architecture RTL;
module tb;
reg I1,I2;
wire O;
ANDGATE DUT (.I1(I1), .I2(I2), .O(O)); // ANDGATE DUT (.*);
endmodule