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How to connect Verliog testbench toa VHDL RTL.

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veer110

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Hi Friends,

Can anyone help me to understand how to connect Verilog TestBench to a VHDL RTL.

It would be great if you can help me with a example.

Thanks,
- Veeresh
 

poluekt

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Exactly as Verilog RTL:

Code:
entity ANDGATE is
  port ( 
    I1 : in std_logic;
    I2 : in std_logic;
    O  : out std_logic);
end entity ANDGATE;
 
architecture RTL of ANDGATE is
begin
  O <= I1 and I2;
end architecture RTL;

module tb;
reg I1,I2;
wire O;

ANDGATE DUT (.I1(I1), .I2(I2), .O(O));  //  ANDGATE DUT (.*);

endmodule
 

FvM

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In addition, your simulator license must include mixed language simulation.
 
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