schnufff
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Hi, I have a design with 5 different and totally isolated cores on one chip. Each core has its on vdd_core/io and vss_core/io. I managed to connect the IO and standard cells correctly. When I do CTS or add Tie-H/L cells in encounter, I need to specify that all Tie-H/L pulling up/down cells from a specific core, should be powered by these cores vcc/vdd. Same for buffers/invertes added by encounter during CTS. Does anyone know a way to accomplish this?
This is something like a multi-supply-voltage desing, but I dont have any power domains or level-shifters, because the cores don't communicate and all have the same supply voltage( but through separated power pins)
thx schnufff
This is something like a multi-supply-voltage desing, but I dont have any power domains or level-shifters, because the cores don't communicate and all have the same supply voltage( but through separated power pins)
thx schnufff