how to connect microblaze to custom VHDL code in ISE

[melexia]

Hi all,

I am generating an EDK project through ISE. I have gone through all tutorials. I have also done adding custom IP whcih can be a VHDL code. But now if I have a huge VHDL logic which is performing all my data acquisition tasks and I have to use a microblaze just for taking this data from VHDL code and transfer it to GUI via USB or ethernet, how would I do it.
I believe that I can use OPB (onchip peripheral bus) but when i click on add IP for OPB it just provides me with clock and reset pins which I surely cannot use for the purpose.
Same happens for PLB4.6 IP also.

Please help I am stuck............

 

[xtcx]

There are more ways to communicate between microblaze and your other RTL components in the design. One of the easy method is to use the GPIO as a memory address map and write\read from your RTL. I'd prefer this way. Generate the GPIO pins as required (Shown below)

ADDR (x-bits)
Data (y-bits)
Wr
Rd
OE

Now, use the addr to select your payload\data structure at the RTL components. I'd do it this way in RTL
Your RTL component may have different payloads. Point each payload with each address.

Paylaod1 - addr XX
Paylaod2 - addr XY

Inside Microblaze if you want to read payload1, you should drive addr with XX and assert Rd signal. In RTL, if Rd is asserted and if addr is XX, you simply connect Payload1 to Data bus of Microblaze GPIO pins.

x-bits depends on how many different maps you require for read\write of payload\data. Y-bits is your data bit width
This we can register memory map.
On the EDK, I believe you have USB\ethernet IP customized with C application. So, in the C application, just create a pointer which points to the GPIO base address of these signals. You can now do I\O transfer at full speed, no matter how bulky the data packet size is !!!, should you require more burst size, increase 32-bit to 64-bit and you can double your throughput
Hope this is your intention
let us know your progress

 

[melexia]

hey thanks for replying. I have implemented it successfully. Currently I have not gone upto full speed data transfer but I got the basic idea.
But still I think that this is a customized solution and not a standard practice, there must be some standard ways for the same e.g.using OPB which I tried to implement but could not........
Once again thanks but please tell me if there is any standard procedure

 

[xtcx]

Well, I would not consider this as a non-standard way. It is one way of customizing. But in your style, if you want it more professional way, then you can still use AXI General purpose IO block to interface your IO transactions directly with your AXI bus or alternatively you can use XPS general purpose IO block to interface with IPIC interface. Well, this is standard. I do not know why you want it with OPB. This block is a part of the OPB, you do not need to access the core bus for interaction while the tool provides a block to interact

 

[melexia]

Well, I would not consider this as a non-standard way. It is one way of customizing. But in your style, if you want it more professional way, then you can still use AXI General purpose IO block to interface your IO transactions directly with your AXI bus or alternatively you can use XPS general purpose IO block to interface with IPIC interface. Well, this is standard. I do not know why you want it with OPB. This block is a part of the OPB, you do not need to access the core bus for interaction while the tool provides a block to interact

Yes it is a way of customizing and easiest also, but I was wondering if there is any standard method which people use. Meanwhile I read about using dual port BRAM and use it on both sides.

thanks and regards,

 

[xtcx]

Good, Please do share the method if you find such!!....

Regards,

 

[knavekid]

There are two ways to set up your FPGA architecture using an embedded Microblaze processor. 1) You can have the Microblaze be the top level of your design and add your custom VHDL code as a Microblaze peripheral. 2) You can have your custom VHDL logic be the FPGA top level design and instantiate the Microblaze as a component.

I recently completed a design using the second technique. For discrete control signals and vectors, I used the Microblaze GPIO and created a custom peripheral of input and output registers. These signals were defined as part of the Microblaze component interface and were connected to my VHDL logic at the top level. I also used dual-port block memory instantiated within my VHDL design and connected one side to the Microblaze component. Using the EDK, I added the block ram interface and routed the memory interface signals as external connections and connected them to the dual port RAM at the top level.

I don't have time to go into more detail of my application, but the FPGA performed digital video processing and used the multi-port memory controller (MPMC) within the Microblaze component for video frame storage into external LPDDR memory. The tutorials were not that useful and I tried many approaches to get everything to work. I started with an AXI design, but had to revert to PLB because the AXI version of the MPMC does not support the MCB memory interface used by my custom VHDL logic.

If your FPGA is intended to be a CPU with some custom interfacing, you should use method 1 with the Microblaze as the top level design. If your FPGA is intended to be a logic array that happens to need a CPU for some control or communications functions, method 2 is better with the logic design at the top level and the Microblaze as a component within the logic design.