How to connect guard ring for esd device

[Kelvintlai]

Hi

I had a ESD NMOS transistor (with sab block) on pwell , which is surrounded with 1st ring (n+/pw), then 2nd middle ring (p+/pw), then 3rd outer ring (n+/dnwell).

My question is when I tried to measure IT2 of the ESD transistor, (with Vd=Vbias, Vg=vs=GND), how do the guard rings connect to?

3rd ring (n+/dnw) : float?
2nd ring (p+/pw) : 0
1st ring (n+/pw) : 0/float?

 

[erikl]

I'd suggest

3rd ring (n+/dnw) : float/VDD
2nd ring (p+/pw) : 0
1st ring (n+/pw) : float/VDD

A VDD connection of the n+ guard rings can raise the whole VDD net well above its normal voltage level - which can absorb a lot of energy during ESD breakdown - if not the VDD protection itself limits this voltage too much. In this latter case, floating n+ rings may be the better solution.

 

[rangermad]

All you may need to do is put your nmos into a deep nwell. Tie the dnwell to VDD. Sometimes the pwell may be tied to GND through a resistor. An outer P+ ring around the whole structure may also be used.