How to configure switch boxes in VHDL in Virtex-5 device?

[msdarvishi]

Hello,

I am wondering if there is a way to cobfigure switch boxes in VHDL, initialize them and connect them consecutively as you wish? I want to connect a series of switch boex together (the output of first is the input of the next), but I do not know is it possible through VHDL or not?

I thank in advance for any kind help and assist.

Regards,

 

[TrickyDicky]

What is this switch box of which you speak?

 

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msdarvishi, are you once again trying to build stuff from the primitive libraries like the delay line using carry4 primitives? Is this switch box you speak of the LUT?

Use LUT1-LUT6, LUT1-6(_D)(_L) and instantiate them in your VHDL code. (note these are the 7 series primitives)

This begs the question: Why would you want to do this!?

 

[msdarvishi]

msdarvishi, are you once again trying to build stuff from the primitive libraries like the delay line using carry4 primitives? Is this switch box you speak of the LUT?

Use LUT1-LUT6, LUT1-6(_D)(_L) and instantiate them in your VHDL code. (note these are the 7 series primitives)

This begs the question: Why would you want to do this!?

@ads-ee, yes I am verifying the possibility of connecting a series of switch boxes consecutively. The switch box that I am talking is that is seen in FPGA Editor, the connection bridge between SLICE.

Motivation : To create a SB chain for a specific application. So , I would need to control the connection between SBs.

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What is this switch box of which you speak?

@TrickyDicky : I am talking is that is seen in FPGA Editor, the connection bridge between SLICE.

 

[ads-ee]

No you can't do this, that is part of the routing matrix, PAR is the one that creates that. There are directed routing constraints (UCF) that can do what you want but not in HDL. As Xilinx knows more about their parts than you or I do writing your own router using directed routing constraints is pretty much a ridiculous thing to do. And designing everything with primitives is an equally silly thing to do.

I'm not sure what you're objective is, but I don't think FPGAs are the correct platform for your use. Given that it seems more like you are trying to abuse what the tools can do instead of just creating a normal HDL design.

 

[vGoodtimes]

You might be able to get what you want by using LOC and RLOC constraints, and then using DIRT constraints after getting them once. The MIG for Virtex-5 from 7 years ago did something like this. IIRC, you can put the DIRT strings into the VHDL code as attributes.

That said, it really sounds like you are hitting a lot of the issues that the FPGA tools are not designed to handle. You might be better off designing this in FPGA editor and then making a netlist and using it as a blackbox in the VHDL.