How to configure 74LS93A to be a modulus-13 counter?

[student2005]

74ls93a

The attached figure shows the internal circuit of 74LS93A. No addition logic gate is required to build a modulus-10 or modulus-12 counter from 74LS93A. Pls advise how to configure 74LS93A to be a modulus-13 counter? Any addition logic gate is required? Thanks.

 

[stalemate]

modulo 10 counter

ya,
i can not show you indetail how to do follow the steps below for deriving the modulo13 counter..
as in the given diagram there are 4 ff.you will be able to perform 16counts
but as we need only 13..we will neglect last three(14,15,16)counts...
so now
1.draw the truth table usimg the a,b,c,d(ops of each ff)
2.draw the timing diagram with clock in the first row,
3. the ff is triggered for active low clock signals,so for every negative trigger
on the ff .. the first ff will toggled .hence its freq will be half the original clock freq.
and similarly second will have one fourth clock freq..
4.check out for last count after that it should start with 0000.. so depending on the
timing diagram decide which gate to be added
regards

 

[Davood Amerion]

counter modulus

Hi
You need a 3 input AND gate.
you must connect Q0, Q2, Q3 to AND gate inputs and connect AND output to 7493 CLEAR inputs (pins 2,3). In this way when counter reach to 13==1101 immidiatly reset to 0000.
and count from 0000, 0001, 0010, ...., 1100, then 0000.
(Also remember connect pin CLKB to Q0).

Regards Davood Amerion

 

[Kral]

timing diagram 74161 counter

Unfortunately, the only inputs (other than the clocks) that you have to work with are the master reset inputs. Decoding the outputs and using the decoder output to trigger the master reset input has the potential for a race condition in which the output may go to an indeterminate state. For example, if you decode the 1101 state and use the decoder output to reset the counter, the decoder output may go back to "0" before all stages of the counter have had a chance to reset.
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Also, consider the transition from 0111 to 1000: Suppose stages A and C are faster than stages B, D. In going from 0111 to 1000, you would have an intermediate transitional state of 1101. This could result in a momentary "trash pulse" from the decoder that might or might not reset the counter..
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If you must use the 74LS93A, the solution may be more complicated than it's worth, but here goes...
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Decode the 1011 state, and use it to set an additional flip-flop on the next clock pulse. Use the additional flip-flop output to reset the counter. Note that the counter will stay in the 0000 state for 2 clock pulses.
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You may be able to get away with using a decoded output to directly reset the counter for hobby or one-of-a-kind applications. I would not use this scheme for production applications where you have to deal with timing differences from chip to chip, as well as temperature dependent AC characteristics.
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The 74LS161 might be a better choice for a modulo X counter. It has a synchronous parallel enable that makes it easy to build a counter with any modulus with no possibility of race problems. The downside is that this device has more pins.