How to compile Al*te*r@ libraries?

Hello,

I am evaluating and learning Q*II 4.0 with model*s**m_SE5.6*. It seems that I have not the precompiled libraries needed and that I must compile them. I would appreciate if someone could explain me how to do this. I have seen many docs in Alt*er@ and Mo*dels*m web but I haven't found how to compile these libraries.

Thanks a lot and best regards,

mimoto

Hello

You can find all libraries which you need in $env(QUARTUS_ROOTDIR)/eda/sim_lib/

First go to Settings Menu, and in a EDA Tool Setings -> Simulation, chose Modelsim (VHDL/Verilog output). After P&R you will have two files
Project_Module.vo (netlist) and Project_Module_v.sdo (SDF file) in simulation/modelsim subdirectory.

next open Modelsim and change dir to simulation/modelsim subdirectory

Example for Startix and Verilog and Gate-Level Timing simulation:

vlib stratix_ver
vlog -work stratix_ver $env(QUARTUS_ROOTDIR)/eda/sim_lib/stratix_atoms.v

#Simulation with SDF file
vlog Project_Module.vo
vlog TB_Module.v
vsim -L stratix_ver -sdftyp /DUT=Project_Module_v.sdo TB_Module

module TB_Module;
...
Project_Module DUT(...);
...
endmodule

For RTL simulation you need (it deepends what kind of alteras blocks you are using) 220model.v/vhd and/or altera_mf.v/vhd

Best reg

perhaps you need compile altera_mf.v and 220model.v as well.

Next commands can be useful:

# atoms compiling (vhdl version):
# $library => library where to compile
# $family => the one we are using
vcom -work $libray ${quartus_path}/eda/sim_lib/${family}_atoms.vhd
vcom -work $libray ${quartus_path}/eda/sim_lib/${family}_components.vhd

# LPM compiling:
vcom -work $libray ${quartus_path}/eda/sim_lib/220pack.vhd
vcom -work $libray ${quartus_path}/eda/sim_lib/220model.vhd

# perhaps we also need megafunctions:
vcom -work $libray ${quartus_path}/eda/sim_lib/altera_mf.vhd
vcom -work $libray ${quartus_path}/eda/sim_lib/altera_mf_components.vhd

Regards

Thanks for the answers. I know have also another problem. My project Design in QII has 4 files:

-eeprom32k.vhd (a simulation model for a eeprom)
-p2s.vhd (the synthetizable .vhd of a serial to parallel epprom converter)
-top.bdf (the top connection between the eeprom32k.vhd and p2s.vhd)
- testbench.vhd (the testbench that apply input to the top.bdf, it instantiates the top in the file).

My problem is that when if I use testbench as the top in the compilation hierarchy and make start->analysis and elaboration the shows
"Wait Statement error at testbench.vhd"
this is the line: wait for TCLK;

Is elaboration similar to synthesis?
I know that my testbench is not synthetizable but should I elaborate before simulation?.

Which are the steps to run model@im directly from quartus becuase in my case start the program all is ok but model@im does not get the correct hierarchy and I just see the command line. The testbench seem that does not run.

Sorry for hitting with so many questions,

thanks a lot and best regards,

mimoto

i believe elobrate is equavalent to syntax checking..