how to come up with insertion delay of the clock path

[hahtesham]

what decides the insertion delay of a design.
In my design for 65nm, I have been constraining the tool to achieve an insertion
delay of 1.3ns because the customer wanted it to be that much. My question is
how did they came up with this value.?

 

[yx.yang]

what decides the insertion delay of a design.
In my design for 65nm, I have been constraining the tool to achieve an insertion
delay of 1.3ns because the customer wanted it to be that much. My question is
how did they came up with this value.?

Hi, hahtesham:
In my opioion, insert delay can be any value if it will not causing function (timing) fail, both internal DFFs and IO timing. While the smaller the better, because when insertion delay is smller is means the depth of clock tree is smaller, then will achieve better power.
Thanks.