type port_array is array(7 downto 0) of std_logic_vector(7 downto 0);
signal my_signal: port_array;
-- package
...
package user_defined_types is
type port_array is array(7 downto 0) of std_logic_vector(7 downto 0);
end user_defined_type
-- application
...
use work.user_defined_types.all; -- your package
entity your_app
port (
input: in port_array;
...
);
end app;
....
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
indexin : in natural range 0 to 7;
datain : in std_logic_vector(7 downto 0);
indexout: in natural range 0 to 7;
dataout : out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
type portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
signal internalregisters: portarray;
begin
internalregisters(indexin) <= datain;
dataout <= internalregisters(indexout);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
clk : in std_logic;
indexin : in natural range 0 to 7;
datain : in std_logic_vector(7 downto 0);
indexout: in natural range 0 to 7;
dataout : out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
type portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
signal internalregisters: portarray;
begin
process(clk)
begin
if rising_edge(clk) then
internalregisters(indexin) <= datain;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
dataout <= internalregisters(indexout);
end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
clk : in std_logic;
write : in std_logic;
indexin : in natural range 0 to 7;
datain : in std_logic_vector(7 downto 0);
read : in std_logic;
indexout: in natural range 0 to 7;
dataout : out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
type portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
signal internalregisters: portarray;
begin
process(clk)
begin
if rising_edge(clk) then
if write = '1' then
internalregisters(indexin) <= datain;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if read = '1' then
dataout <= internalregisters(indexout);
end if;
end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(7 downto 0);
op: in std_logic_vector(2 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
signal zero: std_logic;
begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" => temp := a and b;
when "100" => temp := a and b;
when "001" => temp := a or b;
when "101" => temp := a or b;
when "010" => temp := a + b;
when "110" => temp := a - b;
when "111" => if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others => temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;
end behavioral;
1: process(clk)
begin
2: if rising_edge(clk) then
3: if write = '1' then
4: internalregisters(indexin) <= datain;
end if;
end if;
end process;
tss said:i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?
mar mar lwin said:tss said:i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?
hey who r u ?whic code u using now?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
indexin : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
C: out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
begin
process(clk)
type portarray is array(7 downto 0) of std_logic_vector(7 downto 0); --array is to make 1*8 bit register to 8*8 bit registers
signal internalregisters: portarray; -- 8*8 bit registers
begin
if rising_edge(clk) then
internalregisters(indexin) <= datain; --'datain' store in 8*8 bit registers
a <= internalregisters(indexin) ; --'a' get the data from 8*8 bit registers
b <= internalregisters(indexin) ; -- 'b' get the data from 8*8 bit registers
end if;
end process;
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
clk : in std_logic;
indexin : in std_logic_vector(2 downto 0);
datain : in std_logic_vector(7 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
C : out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
type portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); -- array of byte based registers
signal internalregisters: portarray; -- byte registers
begin
process(clk)
begin
if rising_edge(clk) then
internalregisters(conv_integer(indexin)) <= datain; -- 'datain' store in array of byte registers
-- impossible -> 'A' is defined as 'in' in entity! a <= internalregisters(conv_integer(indexin)); -- 'a' get the data from array of byte registers
-- impossible -> 'B' is defined as 'in' in entity! b <= internalregisters(conv_integer(indexin)); -- 'b' get the data from array of byte registers
end if;
end process;
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" => temp := a and b;
when "100" => temp := a and b;
when "001" => temp := a or b;
when "101" => temp := a or b;
when "010" => temp := a + b;
when "110" => temp := a - b;
when "111" => if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others => temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit is
port(
clk : in std_logic;
indexin : in std_logic_vector(2 downto 0);
datain : in std_logic_vector(7 downto 0);
A : out std_logic_vector(7 downto 0);
B : out std_logic_vector(7 downto 0);
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
C : out std_logic_vector(7 downto 0)
);
END alu8bit;
architecture behavioral of alu8bit is
type portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); -- array of byte based registers
signal internalregisters: portarray; -- byte registers
begin
process(clk)
begin
if rising_edge(clk) then
internalregisters(conv_integer(indexin)) <= datain; -- 'datain' store in array of byte registers
-- impossible -> 'A' is defined as 'in' in entity!
a <= internalregisters(conv_integer(indexin)); -- 'a' get the data from array of byte registers
-- impossible -> 'B' is defined as 'in' in entity!
b <= internalregisters(conv_integer(indexin)); -- 'b' get the data from array of byte registers
end if;
end process;
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" => temp := a and b;
when "100" => temp := a and b;
when "001" => temp := a or b;
when "101" => temp := a or b;
when "010" => temp := a + b;
when "110" => temp := a - b;
when "111" => if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others => temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;
end behavioral;
i try this but it shown the error as below :
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(39): interface object "A" of mode out cannot be read. Change object mode to buffer.
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(39): interface object "B" of mode out cannot be read. Change object mode to buffer.
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 183 megabytes
Error: Processing ended: Sun Jul 19 21:50:21 2009
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings
type portarray is array(2 downto 0) of std_logic_vector(7 downto 0);
signal internalregisters: portarray;
internalregisters(0) -> which is a std_logic_vector(7 downto 0) == 8 bit register
internalregisters(1) -> which is a std_logic_vector(7 downto 0) == 8 bit register
internalregisters(2) -> which is a std_logic_vector(7 downto 0) == 8 bit register
signal internalregisters: array(2 downto 0) of std_logic_vector(7 downto 0);;
signal a, b, c: std_logic_vector(7 downto );
c <= a or b;
c(7 downto 0) <= a(7 downto 0) or b(7downto 0);
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