How to change the default parameter CLKDV_DIVIDE

deebar · Feb 23, 2003

clkdv_divide

Hi,all:
I'm using Xinlinx Spartan II FPGA (XC2S50) for my design.The design flow is XST Verilog.To get a 1/16 frequency of the main clock,i use the DLL,but the DLL's default divide ratio is 2.0,so how to change the parameter CLKDV_DIVIDE? I use the code as follows:
defparam dll_ins.CLKDV_DIVIDE = 16.0;
But the ISE 4.2i gives the error as follows:
ERROR:Xst:1076 - dlldv.v Line 20. Identifier 'CLKDV_DIVIDE' not declared
1 error in compilation
Can anyone help me?

maestor · Feb 23, 2003

clkdv_divide default

Hi deebar,

I usually set the CLKDV_DIVIDE parameter in the UCF. I guess you know what that is and how to assign the UCF file to your design with XST. If not let me know.
Anyway this is what I do and it works:

In your VHDL (for example) you have your DLL:

ibufg_clk_in : ibufg port map (i => clk_in, o => clk_in_i);
--DLL clock MUST be driven by an IBUFG.

i_clkdll : clkdll port map
(
clkin => clk_in_i,
clkfb => clk_out_i,
rst => disabled,
clkdv => clk_dv,
clk0 => clk_out_d
);

bufg_clk_out : bufg port map (i => clk_out_d, o => clk_out_i);

And in your UCF you have:

INST "i_clkdll" CLKDV_DIVIDE = 16;

I hope it helps.

Maestor

How to change the default parameter CLKDV_DIVIDE

deebar

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maestor

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How to change the default parameter CLKDV_DIVIDE

deebar

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