Aug 24, 2006 #1 H hariharan4000 Junior Member level 1 Joined Dec 4, 2005 Messages 15 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,422 Hi i had a question in verilog in an interview. ie.. if u r using nested if-else statements in your code and u find some timing problems. In that case how will u change your code (problem is with the nested if-else). Plz get me the solution.. haran
Hi i had a question in verilog in an interview. ie.. if u r using nested if-else statements in your code and u find some timing problems. In that case how will u change your code (problem is with the nested if-else). Plz get me the solution.. haran
Aug 24, 2006 #2 B bansalr Full Member level 3 Joined Dec 22, 2005 Messages 152 Helped 20 Reputation 40 Reaction score 5 Trophy points 1,298 Activity points 2,165 Re: verilog-- query change the nested if elsif in a clocked process. or try using parallel case if logic permits.
Re: verilog-- query change the nested if elsif in a clocked process. or try using parallel case if logic permits.
Aug 29, 2006 #3 J JaneZhong Newbie level 5 Joined May 14, 2006 Messages 8 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,336 verilog-- query "if-else" will be synthesized to priority level circuit; on the contrary , "case" will be synthesized to parallel circuit.
verilog-- query "if-else" will be synthesized to priority level circuit; on the contrary , "case" will be synthesized to parallel circuit.