How to change the code if I use if-else statements and have timing problems?

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hariharan4000

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Hi
i had a question in verilog in an interview. ie..

if u r using nested if-else statements in your code and u find some timing problems.
In that case how will u change your code (problem is with the nested if-else).

Plz get me the solution..

haran
 

Re: verilog-- query

change the nested if elsif in a clocked process. or try using parallel case if logic permits.
 

verilog-- query

"if-else" will be synthesized to priority level circuit;
on the contrary , "case" will be synthesized to parallel circuit.
 

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