zarax
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Hi everybody,
I'm an Electrical and Electronics Engineering student. For my term project I need to implement an FPGA design which uses VGA interface. Xilinx XSA 3S1000 board has a 100 MHz fixed clock frequency and I need to change that to 25 MHz.
Our instructors and FPGA board datasheet are not helpful. Datasheet say that I need to program CPLD on the board so that it can divide clock frequency. But I have a very limited knowledge on FPGA boards and don't know how to do that. I'm searching the web with my friend and got nothing so far.
Any help appreciated. Thanks.
I'm an Electrical and Electronics Engineering student. For my term project I need to implement an FPGA design which uses VGA interface. Xilinx XSA 3S1000 board has a 100 MHz fixed clock frequency and I need to change that to 25 MHz.
Our instructors and FPGA board datasheet are not helpful. Datasheet say that I need to program CPLD on the board so that it can divide clock frequency. But I have a very limited knowledge on FPGA boards and don't know how to do that. I'm searching the web with my friend and got nothing so far.
Any help appreciated. Thanks.