how to cancel these DC warning, thanks

[tigerajs]

(1)connect to logic 1
(2)connect to logic 1 or logic 0
(3)connected directly to output port

(4Information: Checking no_input_delay...
Warning: The following input ports have no clock_relative delay specified, a default clock is assumed for these input ports. (TIM-208)
--------------------
rst_n

 

[yx.yang]

You can use "suppress_warning TIM-208". For detail, you can man suppress_warning/suppress_message for detail.

 

[tigerajs]

thanks, the (1)(2)(3)warning has been canceled, how to solve the (4)warning

 

[sakthikumaran87]

I think u have to make a proper constraint for this using SDC

 

[tigerajs]

which command , thanks

 

[sakthikumaran87]

sorry i am not very sure... may be set_input_delay

---------- Post added at 07:46 ---------- Previous post was at 07:43 ----------

Hei one more guess is that you have to declare rst_n as Asynchronous reset pin, which will supress this warning. This option is available in linting and hence should be possible in SDC. others can pl comment on this.

 

[tigerajs]

this is reset signal , I think not need input_delay

 

[soloktanjung]

To constraint input signals, you need to use set_input_delay command, e.g. set_input_delay 1.0 [remove_from_collection [all_inputs] [get_ports clk]]. Reset signal is one of the input signal.

Thanks.