how to cancel offset of DC Input signal?

[singhji0000]

i am working on sigma delta ADC and need to cancel offset value of DC input signal.

what are the different methods and how can we implement these using Matlab?

thanks in advance,

manjeet

 

[mikersia]

high pass filtering (analog at the input or digital after Sinc filter), periodical offset correction (analog in integrator), choppering (analog at the input & digital xor at the sigma-delta modulator output).

 

[singhji0000]

thanks for that..

i read in some paper that we can use choppering sequence or fractal sequence [+1 -1 -1 +1] to cancel the offset for 2nd order sigma delta . But i didnt get that idea clear .they have explained it to nullify integrator offset.I want to apply that technique to cancel the input offset voltage.It will be really helpful if u explain me breifly. as i can implement that in matlab then..

regards'
manjeet

 

[mikersia]

use SDM as it is, then add analog modulator in front of SDM under chopper pulse control, and XOR2 at the SDM output (before SINC filter input) with one of it's input connected to chopper pulse control. Chopper pulse frequency should be synchronized with SINC filter output readings. Examples of such structure can be fined e.g. in recent Analog Devices SD ADC.

 

[singhji0000]

do u have the matlab implementation for the same?

it will be of great help and reference.

thanks for ur help

 

[mikersia]

I'm using Verilog

 

[dick_freebird]

If this offset is from a common-mode input offset and
you need to work down to DC then an instrumentation
amplifier front end might be the ticket. If you are only
interested in AC then high-pass filtering is cheaper.
The details are not clear and you need to consider
what you want and what you must reject from the
input. For example is the DC offset internal or external,
fixed or time-varying, what is the highest "junk" and
the lowest "valued" input frequency, etc.

 

[singhji0000]

other then using CDS technique, is there any way to cancel offset in the signal using switch logic circuit?

ofset is generted due to integrator and value is around 10 mV.

 

[mikersia]

what input offset level is enaugh? If Vos~0.5mV...2mV is enaugh, then use CDS or pure analog chopper inside integrator. If Vos<0.1mV is required, then use above described choppering around whole SDM. Last method have limitation of speed - chopper frequency have to be synchronized to ADC conversion and should be less than for other analog methods of offset correction.