how to calculate the upfront fee for a license
omara007 said:
Hi folks ..
Is the price of the IP affected badly by the nature of the IP ? .. for example, is there a big difference in price between a Wireless IP and a Data Compression IP of the same size ? .. is there something like DSP IPs are the most expensive for example ?
Pricing is based on supply&demand. If you are the ONLY company who can offer a super-hot design (like all world-band UWB CMOS transceiver), then you can justify a higher price, and some customers will pay your fee, because they cannot get it anywhere else.
Beyond that, companies come up with completely arbitrary pricing and product packaing schemes. I think you have already thought about this in your post! For example, synthesizeable RTL costs more than a synthesizeable gate-netlist (because the RTL allows the buyer a chance to make high-level architectural modifications.)
And for same reason, a foundry-specific hard-macro (i.e. the IP is delivered to customer as a "GDSII" file) costs less than the synthesizeable gate-netlist -- because the IP can only work with one foundry. (And it's less work for the customer to use in a design, since all the backend work is already done.)
I would also appreciate if you give us your opinions and information about licensing & royalities ..
The major IP-vendors (Synopsys, ARM) offer different pricing structures based on expected customer volume. You could formulate your company's pricing-scheme based on the following made-up example:
Processor 'A__9':
(1) Deliverable option:
Architectural license ($5 million USD) - customer has access to source-RTL, and the legal right to sell silicon product containing modified ARM-implementation to others. (Customer may NOT re-sell architectural IP license to others. In other words, you cannot enter in IP-competition against ARM!)
Synthesizeable netlist ($1 million USD)
GDSII Hard-macro (customer must select target foundry up front) ($250K USD)
With all options, customer has access to 'ARM Reference Flow', which includes floorplan guidelines, DCSH constraint-files, design-for-test guidelines, and simulation (behavioral Verilog) view. Hard-macro option additionally includes all necesary backend views for Cadence Encounter, Synopsys Galaxy, and Magma flows.
(2) per-part or per-wafer royalty
Expect High_volume: $500 thousand USD up-front license-fee
$0.05 recurring fee per device (IC) sold,
or 3% of IC's gross ASP (average selling price), whichever is higher
Expect Mid_volume: $200 thousand USD up-front license-fee
$0.10 recurring fee per device (IC) sold
or 6% of IC's gross ASP, whichever is higher
Expect Low_volume: $100 thousand USD up-front license-fee
$0.20 recurring fee per device (IC) sold
or 10% of IC's gross ASP, whichever is higher
(3) Multi-use license option
Single-use license: Contract covers terms and pricing for use of A__9 in a SINGLE customer tapeout. (Multiple cores in product only affect per-wafer royalty charges, and not deliverable or use-license fee.)
'multi-use': customer pays 1.5 times full price for FIRST tapeout, then discount/reduced price for additional tapeouts. (Other tapeouts can be respins of first tapeout, or totally new designs.) For 3 or more tapeouts, multi-use license is less expensive than individually licensing one-time (repeatedly.)
Multi-use leads to more complex pricing -- generally the IP-vendor offers a family of parts (not just one.) And the customer can get a discount when buying 1 or more different IPs from the same vendor.
// All figures above were imaginary (not based on real-world.) Please take with grain of salt...
But as you can see, the 'per-device' price for an architectural-license, low-volume, single-use A__9 core would cost an arm & leg. On the other hand, a hard-macro, high-volume, multi-use A__9 core would give the customer the best pricing.
<EDIT>
I forgot to add, there's the issue of IP-evaluation, and how to handle that.
Before committing to a large purchase, most customers will want to evaluate your IP. It's a good idea to screen potential customers, and protect your IP by encrypting it, or watermarking it somehow. I suppose at a certain level, you'll just have to 'trust' your customer not to run off with your design. This works better for digital IP-cores -- I'm not sure how an analog IP-core could be 'encrypted.' I would only partner with reputable fabs with good IP-protection policies (like TSMC) -- I think they'll report unauthorized use of analog-IPs, but you need to confirm with TSMC. Of course, if the copier changes the layout sufficiently, then they won't get caught.