How to calculate the magnitude of 1 least significant bit step of 6-bit ADC?

[benji_styler]

Hi, im answering some tutorial practice question on DAC.

Iv worked out that a 6 bit DAC has 64 steps by 2^no.of bits.

How do i work out the magnitude of 1 least significant bit step if the full scale output of the 6 bit DAC is 7V?

Also what is the resolution of a 6 bit DAC?

I cant seem to find any answers to this question...

 

[IanP]

Re: 6 bit DAC?

7V : 64 = 0.109375V .. that is your first step ..

Resolution: This is the number of possible output levels the DAC is designed to reproduce. This is usually stated as the number of bits it uses, which is the base two logarithm of the number of levels. For instance a 1 bit DAC is designed to reproduce 2 levels while an 8 bit DAC is designed for 256 levels. Resolution is related to the Effective Number of Bits (ENOB) which is a measurement of the actual resolution attained by the DAC.

Quoted from:
https://en.wikipedia.org/wiki/Digital-to-analog_converter

Regards,
IanP

 

[benji_styler]

Re: 6 bit DAC?

Thanks for your response.

So the formual is:

(1 least significant bit/ full scale output) x 100%

= (0.109375/ full scale output) x 100%

i cant work out what full scale output is? a little hint please

 

[Weiming]

Re: 6 bit DAC?

One LSB is defined as 1LSB = 7V/64.
And discussing data converters, the term resolution describes the smallest change in the analog output with respect to the value of the reference voltage. But it is slightly different from the definition of LSB in that resolution is typically given in terms of bits. So you DAC resolution is 6bits.
You can see it from Jocob Baker's CMOS: Circuit Design, Layout and Simulation