How to calculate the aligned address

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dll_fpga

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Please help me understand the concept of aligned address and how to calculate it?

I saw the below equation from AXI spec
Aligned_Address = (INT(Start_Address / Number_Bytes) ) x Number_Bytes.
 

If you want to access 4 bytes, your address must be aligned to 4. i.e. 0, 4, 8, 12..

Addresses 1, 2, 3 are non aligned to a 4 byte boundary.
 

jbeniston said:
If you want to access 4 bytes, your address must be aligned to 4. i.e. 0, 4, 8, 12..

Addresses 1, 2, 3 are non aligned to a 4 byte boundary.
Click to expand...

Is it required to be always a power of 2

can it be 0 5 10 to access 5 byte info?
 

Yes, it must be a power of two. See the allowed values for ARSIZE or AWSIZE. There is only one SIZE value that is used for each beat within a burst.
 

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