Re: About max transition
Hi Nantha,
The transition time of a net is the time required for its driving pin to change logic values. This transition time is based on the technology library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load. During optimization, Design Compiler attempts to make the transition time of each net less than the value of the max_transition attribute.
To change the maximum transition time restriction specified in a technology library, use the set_max_transition command. This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting the max_transition attribute on the named objects.
Design Compiler adds buffering to correct the max_transition violations. A common mistake is the assumption that the default_max_transition or the default_max_fanout constraint in the technology library applies to input ports. These constraints apply only to the output pins of cells within the library.Extremely conservative numbers for max_transition, max_fanout, or max_capacitance force Design Compiler to buffer nets excessively.
cheers