how to calculate phase jitter from psd

[xianweng]

hi,all
I have read the file "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" ,which i download from this forum.
I can calculate the period jitter by the matlab code on page 46,but I do not know how to calculate phase jitter using matlab.
Could anyone help figure it out?

thanks any help in advanceView attachment Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.pdf

 

[D.A.(Tony)Stewart]

Is the phase jitter in deg not just the time jitter of the VCO converted to phase? 360 deg/f * Tjitter?

 

[xianweng]

phase jitter is integral of the phase noise of interest bandwith .It is in sec

 

[D.A.(Tony)Stewart]

Phase noise in f domain is used to isolated discrete noise from certain sources to improve design from AWG noise, LO leakage in linear mixers, front end Noise figure etc.

Time Domain jitter is used for correlation with ISI filter response, Asymmetry, magnetic media defects, fading losses etc .

The standard Eye Pattern test and analysis of, clock jitter and synchronized data jitter is used with smart DSO envelopes for permitted jitter.

Time domain margin and frequency domain both can be used to detect ISI , asymmetry and other channel distortion, by comparison with longer symmetrical patterns eg 0101 vs 0011 or with 000010000 vs 11111011111 etc.

Gaussian noise, nonlinear compression and other sources of jitter such as group delay error in filters can be also analyzed in time domain for different data patterns.

The simplest way to,correlate BER and jitter is to,add psuedo-random bit shift early, nom.,late in recovered data to find the error threshold in one packet then 10 or 100 packets or sectors.
One can then extrapolate this for different data patterns to estimate the BER of a channel for a given Tx /Rx level with injected Fading loss.

This can also be inject easily in any clock, data recovery design for production tests to verify adequate noise or jitter margin. One design I have used extensively uses either variable or fixed delay lines with data selected in PRSG mode for early, nom. Late bit shift. e.g. Injecting a 10-20 % of bit period jitter guarantees a certain level of SNR margin as BER vs SNR vs random noise jitter can be correlated to each other in dB/decade of bits received error free to SNR to error free Time Jitter Margin.