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Gain Margin and Phase Margin Bode Plot

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KGF KING

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1738759685126.png

Hi Team,

I'm trying to simulate Stb analysis for my bandgap design. As i concern stb analysis is for simulate the closed loop gain for negative feedback. So my question is how the stable bode plot will look alike and as the arrow pointing in the picture does the starting point for the Loop gain phase start from 0 or start from -180 deg. And if inserted the RC compensation between First stage and second stage of opamp how it will react. is the gain phase will move towards positive value? and how to calculate the RC value?. Someone please enlight me how to make the circuit to stable and high gain. As of now all my device is in saturation point.
 
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A DC coupled circuit with negative feedback must have loop gain starting phase of 180 degree otherwise it can't achieve stable operation point.
--- Updated ---

Is it actually a loop gain plot? It looks more like G=+4 closed loop gain (output/input of an amplifier with internal feedback).
 
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FvM said:
A DC coupled circuit with negative feedback must have loop gain starting phase of 180 degree otherwise it can't achieve stable operation point.
--- Updated ---

Is it actually a loop gain plot? It looks more like G=+4 closed loop gain (output/input of an amplifier with internal feedback).
Click to expand...
Actually this is iprobe was placed at the output of the opamp in a current mode bandgap reference. How does the G=+4 relates to the input or output of the amplifier? (Just to understand the how you analysis the bode plot)
 
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12 dB corresponds to gain of four.
If it's actually loop gain of your band gap circuit, why low frequency gain is so low? Won't expect sufficient regulation.
 
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FvM said:
12 dB corresponds to gain of four.
If it's actually loop gain of your band gap circuit, why low frequency gain is so low? Won't expect sufficient regulation.
Click to expand...
Yeah that's why, i'm trying to learning how to optimise the circuit to achieve the gain.
 
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Can you post a circuit schematic to let us understand how the gain is established? I still wonder if iprobe is placed wrongly.
 
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FvM said:
Can you post a circuit schematic to let us understand how the gain is established? I still wonder if iprobe is placed wrongly.
Click to expand...
1738917411321.png

Since i already post the circuit i also like to review regarding the design because with this design it's quite hard to maintain the Id and what is the flaw in these design if we try to design across the PVT variations? P/S: M9 is the gate and drain is connected.
 
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I can't see how OP output is controlling bandgap current. In the shown schematic, neither left nor right side gate bias rails are driven.
I would expect M7.drain controlling the current source.
 
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1739175123561.png

Yes, sorry i missed that point. It's a current mode bandgap so i designed to generate 0.5uA so i planned to self bias the current mirror.
 
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