entity shifter is
port (
------------------------------------------------------------
--Clock and reset
------------------------------------------------------------
clk : in std_logic;
a : in std_logic;
b : out std_logic
);
end entity;
architecture rtl of shifter is
signal temp : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp(14 downto 0) & a;
end if;
end process;
b <= temp(15);
end rtl;
hi trickydicky.
is quartus is better than xilinx?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?