how to calculate LUT usage in fpga design?

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Junior Member level 3
Hi All,

The logic count in a fpga/asic is considered as a number of 4-LUT usage now a days. I have doubt in calculating the number of 4-LUTs for any design, how can we calculate it? Is it depends on number of inputs or number of outputs?

Also how many 4-LUTs will be used if i design 16-bit shift register and 4-bit adder?

Thanks...

kirill

Member level 5
The system which you are using should generate some reports about the usage of a die, try to find it

Junior Member level 3

That's true. I counted no. of LUTs by that way also. It is showing 18 LUTs and 16 FFs for 16-bit shift register. In that i got 16 no. of FFs but i didn't get how it is using 18-LUTs (4-input) for it.

kirill

Member level 5
Also the system should generate graphic scheme which will show you why synthesizer use 18 LUTs

Junior Member level 3
Yes Kirill, I also refered its schematic and technology map viewer. but it is showing the design using different no. of input LUT not 4 input LUTs. I want to know how the tool is calculating resourse usage with respect to 4 input LUTs.

kirill

Member level 5
Synthesizer parses your hdl code and applies optimization algorithms(i suppose that you will not find any information which algorithms system uses) and than your combinational logic transalates into LUTs. LUT is like multiplexer and its inputs are address.

Junior Member level 3
I know that LUT construction and its basic but i am not getting how tool has implemented it into 18 LUTs. which value it will store at which location? how many inputs are required for implementing 16 bit shift register? how many outputs are required? how LUTs will be connected to each other? I want to know these things...

Thanks

kirill

Member level 5
I think that hardly anyone can help you in why suthesizer translates in 18 luts not in 17, you work with final compiler and you can not change it, only input compiler parameters(hdl code, sythesizer options) affects on your result. And what goal are you seeking? You want to reduce usage of a die?) If no, never mind it

Junior Member level 3
No i am not reducing die resources... I just wanted to know for my knowledge.

dcreddy1980

Full Member level 5
Lets take a small example :

If you have written the below code where you are trying to do XOR of all your 6-bit input vector

o/p = inp(0) ^ inp(1) ^ inp(2) ^ inp(3) ^ inp(4) ^ inp(5)

I wll split in to temporary signals to map in to LUT :

o/p1 = inp(0) ^ inp(1) ^ inp(2) ^ inp(3)
o/p2 = o/p1 ^ inp(4) ^ inp(5)
o/p = o/p2

you could see that o/p1 will be 1-LUT4 and o/p2 will be 1-LUT3

So in general u need 1-LUT4 + 1-LUT3

Let me know if you need further explanation

sanju_

sanju_

Points: 2

TrickyDicky

Why not post your code? then it might be a bit clearer

Junior Member level 3
dcreddy:
same thing can you explain for 16-bit shift register?

TrickyDicky:
Actually this is for clearing a doubt not for perticular code. Then also you can consider 16-bit shift register as my code.

TrickyDicky

The thing is, code can be important. Ive just built the following shift register code and it uses 16 registers and 0 LUTs.

Code:
entity shifter is

port (

------------------------------------------------------------
--Clock and reset
------------------------------------------------------------
clk                       : in  std_logic;

a  : in std_logic;

b : out std_logic
);
end entity;

architecture rtl of shifter is
signal temp : std_logic_vector(15 downto 0);
begin

process(clk)
begin
if rising_edge(clk) then
temp <= temp(14 downto 0) & a;
end if;
end process;

b <= temp(15);
end rtl;

So I wonder what you are doing.

Junior Member level 3
i'm adding my code here and i have synthesized it using xilinx ISE tool.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity shift_reg is
port(

clk : in STD_LOGIC;
clr : in STD_LOGIC;
data_ld : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
shift_in : in STD_LOGIC;
shift_en : in STD_LOGIC;

shift_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (15 downto 0)

);

end shift_reg;

architecture definition of shift_reg is

constant RESET_ACTIVE : std_logic := '0';

signal data_int : STD_LOGIC_VECTOR (15 downto 0);

begin

process(clk, clr)
begin

if (clr = RESET_ACTIVE) then
data_int <= (others => '0');
elsif clk'event and clk = '1' then
if (data_ld = '1') then
data_int <= data_in;
elsif shift_en = '1' then
data_int <= data_int(14 downto 0) & shift_in;
end if;
end if;
end process;

shift_out <= data_int(15);
data_out <= data_int;

end definition;

TrickyDicky

then its clear why the LUTS are used - to generate the muxes that perform the load.

sanju_

Points: 2

Points: 2

Junior Member level 3
you mean to load data into data_out?

also which tool are u using?

TrickyDicky

Im using quartus - and for your code, I got 16 regs and 16 Luts - as expected.

The muxes are generated for the "if data_ld = '1' then" condition, as the registers should have a clock enable input. data_int is really just an imaginary signal that connects the data in to the data out.

Basically, the muxes chose between data_in or data_int(n-1) for each bit, with the selection controlled by data_ld. This is where your LUTs are coming from.

sanju_

Points: 2

Points: 2

sanju_

Full Member level 3
hi trickydicky.
is quartus is better than xilinx?

Junior Member level 3
Thank you TrickyDicky....

Thanks again for your quick support.

TrickyDicky

hi trickydicky.
is quartus is better than xilinx?

Two different manufactureres. Quartus only compiles for altera products, ISE only for Xilinx.

sanju_

Points: 2