by using spice simulation the min delay (setup time) required between data and clock so that data is captured to output is calculated.
DATA __ __/```````\___
CLK _/``\__/``\__
OP _______/`````
for example, the simulation is done in number of steps by decreasing delay between data and clock. in each it verify the output (should be 1 in above case). in this way the min time between between clk and data pin gives the steup time.