I am having Problem with my code that total power consumed in one clock is less than the leakage power. This means that dynamic power consumed in that clock will come negative. I m attaching the code and waveforms....(upper waveform is input & lower waveform is clock)
vdd 12 0 dc 1v
***********Delay Calculation********************
vin 1 0 ac pulse(0v 1v 0.35ns 0.1ns 0.1ns 0.95ns 2ns )
vclk 2 0 ac pulse(0v 1v 0.4ns 0.1ns 0.1ns 0.5ns 1ns )
************************************************
***********Leakage Power Calculation(in,clk = 1,1)********************
*vin 1 0 dc 1v
*vclk 2 0 dc 1v
**************************************************************
*inverter1*
mni1 4 1 0 0 nmod w=90nm l=50nm
mpi1 4 1 12 12 pmod w=180nm l=50nm
*inverter2*
mni2 5 7 0 0 nmod w=90nm l=50nm
mpi2 5 7 12 12 pmod w=180nm l=50nm
*inverter3*
mni3 7 6 0 0 nmod w=90nm l=50nm
mpi3 7 6 12 12 pmod w=180nm l=50nm
*inverter4*
mni4 8 7 0 0 nmod w=90nm l=50nm
mpi4 8 7 12 12 pmod w=180nm l=50nm
*inverter5*
mni5 10 11 0 0 nmod w=90nm l=50nm
mpi5 10 11 12 12 pmod w=180nm l=50nm
*inverter6*
mni6 11 9 0 0 nmod w=90nm l=50nm
mpi6 11 9 12 12 pmod w=180nm l=50nm
*inverter-clock*
mniclk 3 2 0 0 nmod w=90nm l=50nm
mpiclk 3 1 12 12 pmod w=180nm l=50nm
*transmission-gate1*
mnt1 6 3 4 0 nmod w=180nm l=50nm
mpt1 4 2 6 12 pmod w=360nm l=50nm
*transmission-gate2*
mnt2 6 2 5 0 nmod w=180nm l=50nm
mpt2 5 3 6 12 pmod w=360nm l=50nm
*transmission-gate3*
mnt3 9 2 8 0 nmod w=180nm l=50nm
mpt3 8 3 9 12 pmod w=360nm l=50nm
*transmission-gate4*
mnt4 9 3 10 0 nmod w=180nm l=50nm
mpt4 10 2 9 12 pmod w=360nm l=50nm
.lib "45nm-bulk" cmos_models
.tran 1ps 5ns
.plot tran v(2) v(11)
************total Power Calculation(op =High)*****************
.meas tran itotal AVG i(vdd) FROM=0.4ns TO=1.4ns
.meas Etotal PARAM='-1*itotal'
**********************************************************
*.op
.option post
.probe
.end