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It is d flip-flop. Its dynamic power consumption depends on CLK's frequency. Higher frquency leads to higher power consumption.
It comes from gate capacitor charging and discharging.
Also D signal also affects power consumption.
It is better to have simulation for better estimation.
Add supply voltage source first. Set supply voltage for practical application.
Add periodical signal for CK.
If you are not sure about the application, just connect QB to D as 1/2 frequency divider.
Here, QB is input of I6.
And run HSPICE and probe the current of the supply voltage.
I am not able to understand your answer. If you can elaborate your answer, it would be better for me.... can i calculate leakage power if i connect 0 to both clock and input and then calculating current across Vdd???????
If supply voltage is constant, you can use average current multiflying voltage to get the power.
Otherwise, you should integrate product of current and voltage thru time for average power.
Thanks for your reply.... i wanted to ask one more thing related to dynamic power. the circuit for i want to calculate power is positive edge triggered D filp-flop. when we will apply waveforms at D-input and clock, there may be the conditions in one clock cycle when clock is zero and input is switching. i want to ask that power related to this condition will be considered as dynamic power or not????
I am having Problem with my code that total power consumed in one clock is less than the leakage power. This means that dynamic power consumed in that clock will come negative. I m attaching the code and waveforms....(upper waveform is input & lower waveform is clock)
Even if your simulation is correct, it can't be concluded as that. When you simulate dynamic condition, the voltage condition is not exact as that for leakage power simulation. So it is possible leakage power in dynamic condition is smaller than that in static case.
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