Roughly, in general, 1um net witdh could support 1mA.
The question is how much high the pic of current is?
Generaly if you have a clock design, after the rising edge all flops will consumme during the "skew" delay, and the combinational logic will change function of the new value in the flops.
1-Empiric way, you know the worst consumption cases, and you used it to test the IR Drop on VSS & VDD source.
2-If it is a fix function module, like switch/interface..., you could simulate the application and used power tool (like PrimeTime PX) to know the worst pic of power consumption, or the level after is to see in power tool like Encounter where are the power consumption and see the power consumption over the design.