U can look up the synopsys's .lib and take
a look at the 2 input nand's area value.
For TSMC .35 Silicide , it's 1. That means it represent as one gate count.
For TSMC .35 Policide , it's 70. That means it represent as 70 um * um .
As rh1101 said , the routing resource affect a lot on the final area. Depends on how many metals u utilize, how's the congestion based on ur floor-plan and the power stripe , the final routing utilization and so on. So u should consult ur layout engineer to have the final chip area.
BTW , u may call one of the design service's company, such as Faraday , Goya, or GlobalUnit chip. Just tell the sales ur gate count and the sram spec. , they will estimate the die size and the price based on their experienced formula.