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I don't think there is a formula to calculate die size just based on gate count and RAM size. If you look at most chip, you will see that about 25%~40% of die size is used for just routing purposes. That means die size depends largely on unknown factors such as cell library used, routing tools, and maybe experiences of routing engineers. You can only do some comparison with known chip design with different gate count, RAM size to get rough idea about the die size of a new design.
U can look up the synopsys's .lib and take
a look at the 2 input nand's area value.
For TSMC .35 Silicide , it's 1. That means it represent as one gate count.
For TSMC .35 Policide , it's 70. That means it represent as 70 um * um .
As rh1101 said , the routing resource affect a lot on the final area. Depends on how many metals u utilize, how's the congestion based on ur floor-plan and the power stripe , the final routing utilization and so on. So u should consult ur layout engineer to have the final chip area.
BTW , u may call one of the design service's company, such as Faraday , Goya, or GlobalUnit chip. Just tell the sales ur gate count and the sram spec. , they will estimate the die size and the price based on their experienced formula.
1) The design may be pad limited, that is, the size of the
die is controlled by the number of pins. Because all the
I/O cells are located on the boundary of the die, a high
number of pins may cause the die to be bigger than
the logic will otherwise requires.
2) There is extra logic required for test: SCAN and BIST. This
may increase the total gate count by 5 to 15%.
I don't think you can figure out the die size from gate counts. There are several ways which will affect your die size:
1. Row utilization.
2. IO to core distance(X and Y).
3. Core to Block distance.
BTW, it depends on pad limited or core limited
I think estimation means it is not quite correct.
and this data is only for other team's reference.
RAM die size can be getten from RAM specification and congestion factor is not consided.
Gate count is caculated with 2-nand area and synthesis area addition congestion (from other projects experience). it depends on the technology.