vlsi_whiz
Full Member level 4
cell area calculate
If you've done IC layout, be it Analog or Digital/ASIC, you will wonder how to calculate the cell area. Well, here are some rules from which you can calculate the area...
1. Resistor Area:
\[Ar = 1.2RWr(Wr + Sr) / Rs\]
Where:
R = Desired Resistance
Rs = Sheet Resistance
Wr = Width of the Resistor
Sr = Spacing between adjacent stripes
2. Capacitor Area
\[Acap = C / Cunit-area\]
3.MOS Transistor
\[Amos = 1.3Wg(Lg + Sgg)\]
Where:
Wg = width of the gate
Lg = length of the gate
Sgg = space between adjacent stripes of a multifinger transistor
4. Cell Area
\[Acell = PfΣA\]
Where Pf is the packing factor and is about 1.5 to 2.0 for CMOS technology.
If you've done IC layout, be it Analog or Digital/ASIC, you will wonder how to calculate the cell area. Well, here are some rules from which you can calculate the area...
1. Resistor Area:
\[Ar = 1.2RWr(Wr + Sr) / Rs\]
Where:
R = Desired Resistance
Rs = Sheet Resistance
Wr = Width of the Resistor
Sr = Spacing between adjacent stripes
2. Capacitor Area
\[Acap = C / Cunit-area\]
3.MOS Transistor
\[Amos = 1.3Wg(Lg + Sgg)\]
Where:
Wg = width of the gate
Lg = length of the gate
Sgg = space between adjacent stripes of a multifinger transistor
4. Cell Area
\[Acell = PfΣA\]
Where Pf is the packing factor and is about 1.5 to 2.0 for CMOS technology.
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